Design of any electronic circuit requires reconciliation of power supply and components to ensure that the device will function without mishap. Simulators currently exist which enable a computer-based simulation of the connectivity of an application-specific integrated circuit (ASIC) or system-on-chip (SoC). These simulators allow testing of the connectivity of pins within the circuit and check that the voltage provided to each pin is matched to the voltage requirement of the pin with a static checker tool. The simulator conducts a static verification of the power intent by simulating a power supplied through the elements of the circuit by a voltage transmitted from a power source.
Static low power checking is traditionally accomplished by defining a set of rules which are tested against a circuit design to determine if the design conforms to the rules. For power supply checking, this includes determining if a power supply of an ASIC is correctly connected to a particular pin.
The currently implemented simulator systems enable a user to place a plurality of pins and connections within an ASIC and to simulate the power through the ASIC. In some such simulators, a unified power format (UPF) file is created which formally describes the power intent of the system which is checked against the actual system implementation design by the static checking tool. The simulator models and verifies the system power distribution network prior to production of the system, and power supply errors can be quickly identified. The static checking tool confirms that the implementation of the ASIC matches the rules defined by the formal description of the power intent in the UPF file.
An ASIC includes millions of electrical connections which must be accounted for in the power testing system. For this reason, the systems which enable the simulation of ASICs or SOCs include the ability to check for a minimal number of features—expected and received voltage at a pin and connection type—in order to provide efficient testing of the connectivity of the circuit. Because of the number of connections which are checked by the static checking tool, it would not be feasible to extend the number of features without substantially increasing the computing time required for the static checker tool. Further, the complexity of individual components within a larger system such as a device or power supply system is much greater than individual logic gates in an ASIC. The current simulators are not able to be generalized to accommodate larger systems described by and including electronic circuits, such as solid state devices, printed circuit board (PCB) systems, power delivery networks, or even larger scaled complex electrical systems such as cars, because of the much greater complexity of the functionality of the voltages and signals on the pins and connections which would be needed to be described to test these systems in the current simulation software, which present UPF file formats are unable to provide.
Accordingly, there is need to correct the problems inherent to present day circuit simulation software systems.